1. Field of the Invention
The present invention relates to a surface discharge AC plasma display panel, a method of driving same and a plasma display apparatus employing same.
2. Description of the Related Art
The plasma display panel (PDP) has good visibility because it generates its own light, is thin and can be made with large-screen and high-speed display. For these reasons it is attracting interest as a replacement for the CRT display. A surface discharge AC PDP is especially suitable for full color display. Therefore, there are high expectations in the field of high-vision and the demand for a higher quality image is increasing. A higher quality image is achieved by generating higher definition, a higher number of gradations, better brightness, lower brightness for black areas, higher contrast and the like. High definition is achieved by narrowing the pixel pitch, a higher number of gradations is achieved by increasing the number of subfields within a frame, higher brightness is achieved by increasing the number of times a sustaining discharge is performed, and lower brightness for deeper blacks is achieved by reducing the quantity of light emission during the reset period.
FIG. 30 shows the schematic structure of an surface discharge AC plasma display panel (PDP) 10P in the prior art.
On the observer-side of one of the glass substrates that face each other, electrodes X1 to X5 are formed in parallel to one another at an equal pitch, and electrodes Y1 to Y5 are formed in parallel to one another to form parallel pairs with the corresponding electrodes X1 to X5. On the other glass substrate, address electrodes A1 to A6 are formed in the direction that runs at a right angle to the aforementioned electrodes, and phosphor covers on that. Between the glass substrates that face each other, partitioning walls 171 to 177 and partitioning walls 191 to 196 are arranged intersecting each other in a lattice, to ensure that no erroneous display is made through discharge of one pixel affecting adjacent pixels.
The surface discharge PDPs have an advantage in that the phosphor does not become degraded due to the impact of ions on it since discharge occurs between adjacent electrodes on the same surface. However, since a pair of electrodes is provided for each of the display lines L1 to L5, the degree to which the pixel pitch can be reduced is limited and this is a stumbling block for achieving high definition. In addition, the scale of the drive circuit must be large since there is a high number of electrodes.
To deal with this problem, a PDP 10Q as shown in FIG. 31 has been disclosed in Japanese Patent Publication No. 5-2993 and No. 2-220330.
In the PDP 10Q, partitioning walls 191 to 199 are provided on the central lines of the electrodes X1 to X5 and Y1 to Y4, which are surface discharge electrodes, and these electrodes, except for the electrodes X1 and X5 at the two sides, i.e., the electrodes X2 to X4 and the electrodes Y1 to Y4, are commonly used by display lines that are adjacent in the direction of the address electrodes. With this, the number of electrodes is almost halved and the pixel pitch can be reduced, achieving higher definition compared to the PDP shown in FIG. 30. In addition, the scale of the drive circuit can also be halved.
However, in the publications cited above, since write is performed in linear sequence for the display lines L1 to L8, the discharge would affect adjacent pixels in the direction of the address electrodes if the partitioning walls 191 to 199 are omitted, resulting in erroneous display. Thus, the partitioning walls 191 to 199 cannot be omitted and this presents an obstacle to achieving higher definition by reducing the pixel pitch. In addition, it is not easy to provide the partitioning walls 191 to 199 on the central lines of the electrodes and, as a result, the PDP 10Q will be expensive to produce. Furthermore, in the publications mentioned above, a specific waveform of the voltage to be applied to the electrodes is not disclosed and, as a result, the invention has not been put into practical use. In order to make it possible to remove the partitioning walls running in the direction of the surface discharge electrodes, the distance between the electrodes at the two sides of each of the partitioning walls 191 to 196 must be increased in the structure shown in FIG. 30, so as to reduce the effect of their electric fields between that electrodes. Consequently, the pixel pitch increases, preventing achievement of higher definition. For instance, the distance between the electrodes Y1 and X2 (non display line) is 300 xcexcm when the distance between the electrodes Y1 and X2 (display line) is 50 xcexcm.
In addition, during the reset period, light is emitted because of the whole-screen (all pixel) discharge and brightness in the black display areas is increased, reducing the quality of the display.
Moreover, since the color of the phosphor is white or bright gray, incident light from the outside is reflected on the phosphor at non display lines when observing an image on the PDP in a bright place, lowering the contrast of the image.
In addition, since only one line can be addressed at a time, the address time cannot be reduced, and it is not possible to achieve a higher number of gradations by increasing the number of subfields or to achieve higher brightness by increasing the number of times the sustaining discharge is performed.
Accordingly, a comprehensive object of the present invention is to provide a plasma display panel, a method of driving same and a plasma display apparatus, all of which achieve a higher quality image.
To put it concretely, a first object of the present invention is to provide a method of driving a plasma display panel and a plasma display apparatus, which achieve higher definition by further reducing the pixel pitch.
A second object of the present invention is to provide a plasma display panel, a method of driving the same and a plasma display apparatus that can increase black display quality reduced by whole-screen (all pixel) discharge light emission during a reset period.
A third object of the present invention is to provide a plasma display panel, a method of driving the same and a plasma display apparatus that can increase image contrast by decreasing the reflected light from a non display line.
A fourth object of the present invention is to provide a plasma display panel, a method of driving the same and a plasma display apparatus that can increase the number of gradations and brightness by addressing plural display lines simultaneously to decrease the address period.
According to the first aspect of the present invention, there is provided a plasma display apparatus comprising: a plasma display panel having a substrate, electrodes X1 to Xn+1 formed at the substrate, electrodes Y1 to Yn formed at the substrate and address electrodes formed at the substrate or at another substrate facing the substrate at a distance, the electrodes X1 to Xn+1 being arranged in that order and parallel to one another, an electrode Yi being arranged between an electrode Xi and an electrode X+1 for each i=1 to n, the address electrodes being arranged intersecting the electrodes X1 to Xn+1 and Y1 to Yn at a distance; and an electrode drive circuit; wherein the electrode drive circuit includes: first field addressing means, for i=1 to n, for causing a first address discharge to occur between the electrode Yi and the address electrodes selected in correspondence to display data in a first field of a frame and for causing a discharge to occur between the electrode Yi and the electrode Xi using the first address discharge as a trigger to generate a first wall charge required for a sustaining discharge in correspondence to the display data in the first field; first field sustaining means, after the first wall charge has been generated and for odd number o among 1 to n and for even number e among 1 to n, for supplying a first AC sustaining pulse between an electrode Yo and an electrode Xo and for supplying a second AC sustaining pulse between an electrode Ye and an electrode Xe; second field addressing means, for i=1 to n, for causing a second address discharge to occur between the electrode Yi and the address electrodes selected in correspondence to display data in a second field of the frame and for causing a discharge to occur between the electrode Yi and the electrode Xi+1 using the second address discharge as a trigger to generate a second wall charge required for a sustaining discharge in correspondence to the display data in the second field; and second field sustaining means, after the second wall charge has been generated and for odd number o among 1 to n and for even number e among 1 to n, for supplying a third AC sustaining pulse between the electrode Yo and the electrode Xo+1 and for supplying a fourth AC sustaining pulse between the electrode Ye and the electrode Xe+1.
With the first aspect of the present invention, since the display lines in odd-numbered fields and the display lines in even-numbered fields can be made so as not to affect each another in regard to discharge, it is not necessary to provide partitioning walls along the central lines on the electrodes X1 to Xn+1 and electrodes Y1 to Yn of the plasma display panel. Thus, production of the plasma display panel is facilitated, reducing the production cost and, with the pixel pitch reduced, higher definition can be achieved.
In the first mode of the first aspect of the present invention, the first field sustaining means supplies the first and second AC sustaining pulses while ensuring that voltage waveforms applied to the electrodes Yo and Xe are of the same phase to each other, that voltage waveforms applied to the electrodes Ye and Xo are of the same phase to each other and that the first and second AC sustaining pulses are of the reverse phase to each other; and the second field sustaining means supplies the third and fourth AC sustaining pulses while ensuring that voltage waveforms applied to the electrodes Yo and Xo are of the same phase to each other, that voltage waveforms applied to the electrodes Ye and Xe are of the same phase to each other and that the third and fourth AC sustaining pulses are of the reverse phase to each other.
The first mode is effective since the display lines in odd-numbered fields and the display lines in even-numbered fields do not affect each other in regard to discharge.
In the second mode of the first aspect of the present invention, the first field addressing means, in a first period, applies a DC voltage to all odd-numbered electrodes among the electrodes X1 to Xn+1 and applies a pulse with a reverse polarity voltage against the DC voltage to the electrode Yo, and in a second period, applies the DC voltage to all even-numbered electrodes among the electrodes X1 to Xn+1 and applies a pulse with a reverse polarity voltage against the DC voltage to the electrode Ye; and the second field addressing means, in a third period, applies the DC voltage to all the even-numbered electrodes among the electrodes X1 to Xn+1 and applies a pulse with a reverse polarity voltage against the DC voltage to the electrode Yo, and in a fourth period, applies the DC voltage to all the odd-numbered electrodes among the electrodes X1 to Xn+1 and applies a pulse with a reverse polarity voltage against the DC voltage to the electrode Ye.
With the second mode, only one pulse with a large width needs to be supplied to each of the odd-numbered group and the even-numbered group of the electrodes X1 to Xn+1 during each address period for the odd-numbered fields and the even-numbered fields. Thus, power consumption is reduced compared to a case in which the pulse must be supplied to those groups for every scan of the electrodes Y1 to Yn. In addition, the structure of the electrode drive circuit can be simplified.
In the third mode of the first aspect of the present invention, the first field addressing means applies pulses with reverse polarity voltages to each other to the electrodes Yi and Xi when causing the discharge to occur between the electrode Yi and the electrode Xi; and the second field addressing means applies pulses with reverse polarity voltages to each other to the electrodes Yi and Xi+1 when causing the discharge to occur between the electrode Yi and the electrode Xi+1.
With the third mode, since only the required pulse is supplied to the electrodes X1 to Xn+1 during an address period, power consumption is reduced compared to a case in which pulses are commonly supplied to the odd-numbered group and the even-numbered group among the electrodes X1 to Xn+1.
In the fourth mode of the first aspect of the present invention, the first and second field addressing means includes: a first sustain circuit for outputting a first voltage-waveform of a DC pulse train; a second sustain circuit for outputting a second voltage-waveform with its phase offset by 180xc2x0 from a phase of the first voltage-waveform; a switching circuit having switching elements for selectivity supplying either the first or second voltage-waveform to the electrodes Yo, Ye, Xo and Xe; and a control circuit for controlling the switching elements of the switching circuit in such a way that the first voltage-waveform is supplied to the electrodes Yo and Xe and the second voltage-waveform is supplied to the electrodes Ye and Xo after the first wall charge has been generated and that the first voltage-waveform is supplied to the electrodes Ye and Xe after the second wall charge has been generated.
With the fourth mode, since the voltage-waveforms from the first sustain circuit and the second sustain circuit are selectively supplied to the electrodes Yo, Ye, Xo and Xe, the structure of the electrode drive circuit is simplified.
In the fifth mode of the first aspect of the present invention, both the first field and the second field consist of a plurality of subfields with numbers of sustaining discharge pulses different from one another, and the electrode drive circuit further comprising: first field reset means, prior to the first address discharge in a first subfield of the first field and for i=1 to n, for causing a discharge to occur between the electrode Yi and the electrode Xi and between the electrode Yi and the electrode Xi+1 in order to eliminate wall charge for all pixels or to generate wall charge for all pixels; and prior to the first address discharge in the rest of the subfields of the first field and for odd number o among 1 to n and for even number e among 1 to n, for causing a discharge D1 to occur between the electrode Yo and the electrode Xo and a discharge D2 to occur between the electrode Ye and the electrode Xe with a time lag from the discharge D1 in order to eliminate or generate wall charge only for pixels in the first field; and second field reset means, prior to the second address discharge in a first subfield of the second field and for i=1 to n, for causing a discharge to occur between the electrode Yi and the electrode Xi and between the electrode Yi and the electrode Xi+1 in order to eliminate wall charge for all pixels or to generate wall charge for all pixels; and prior to the second address discharge in the rest of the subfields of the second field and for odd number o among 1 to n and for even number e among 1 to n, for causing a discharge D3 to occur between the electrode Yo and the electrode Xo+1 and a discharge D4 to occur between the electrode Ye and the electrode Xe+1 with a time lag from the discharge D3 in order to eliminate or generate wall charge only for pixels in the second field.
With the fifth mode, since unwanted light emission is reduced, the brightness of black display is lowered to improve the black display quality.
In the sixth mode of the first aspect of the present invention, each of the electrodes X1 to Xn+1 and Y1 to Yn includes: a transparent electrode formed at the substrate; and a metal electrode formed at the transparent electrode along the central line of the transparent electrode with a width smaller than the transparent electrode.
With the sixth mode, the structure of each display line is made identical.
According to the second aspect of the present invention, there is provided a plasma display apparatus comprising: a plasma display panel having a substrate, electrodes X1 to X2n formed at the substrate, electrodes Y1 to Yn formed at the substrate and address electrodes formed at the substrate or at another substrate facing the substrate at a distance, electrodes Xo, Yi and Xe being arranged in that order parallel to one another, where o=2ixe2x88x921, e=2i and i=1 to n, the address electrodes being arranged intersecting the electrodes X1 to X2n and Y1 to Yn at a distance; and an electrode drive circuit; wherein the electrode drive circuit includes: odd-numbered frame addressing means, for o=2ixe2x88x921 and i=1 to n, for causing a first address discharge to occur between the electrode Yi and the address electrodes selected in correspondence to display data in an odd-numbered frame and for causing a discharge to occur between the electrode Yi and the electrode Xo using t he first address discharge as a trigger to generate a first wall charge required for a sustaining discharge in correspondence to the display data in the odd-numbered frame; odd-numbered frame sustaining means, for o=2ixe2x88x921 and i=1 to n, for supplying a first AC sustaining pulse between the electrode Yi and the electrode Yo after the first wall charge has been generated; even-numbered frame addressing means, for e=2i and i=1 to n, for causing a second address discharge to occur between the electrode Yi and the address electrodes selected in correspondence to display data in an even-numbered frame and for causing a discharge to occur between the electrode Yi and the electrode Xe using the second address discharge as a trigger to generate a second wall charge required for a sustaining discharge in correspondence to the display data in the even-numbered frame; and even-numbered frame sustaining means, for e=2i and i=1 to n, for supplying a second AC sustaining pulse between the electrode Yi and the electrode Ye after the second wall charge has been generated.
With the 2nd aspect of the present invention, since the display lines in the odd-numbered frames and the display lines in the even-numbered frames can be made not to affect each other in regard to discharge, it is not necessary to provide partitioning walls along the central lines of the electrodes Xo, Yi and Xe of the plasma display panel. Thus, production of the plasma display panel is facilitated, reducing the production cost and allowing reduced pixel pitch, which supports higher definition.
Also, since two display lines are formed with three parallel electrodes, the pixel pitch can be reduced compared to the prior art structure in which two display lines are formed with four parallel electrodes, making it possible to achieve higher definition. In addition since it is not necessary to divide the electrodes Y1 to Yn into even and odd numbered groups, the structure is simplified.
Moreover, with frame interlaced scanning, the address period can be reduced by half compared to that with non-interlaced scanning, lengthening the period of sustaining discharge. This makes it possible to achieve a higher number of gradations by increasing the number of sub frames or makes it possible to achieve higher brightness by increasing the number of times the sustaining discharge is performed.
In the first mode of the second aspect of the present invention, the electrodes Xo, Yi and Xe have substantially symmetrical forms relative to a central line of the electrode Yi; each of the electrodes has a transparent electrode formed at the substrate, and a metal electrode formed at the transparent electrode at a width smaller than that of the transparent electrode; and the metal electrodes of the electrodes Xo and Xe are arranged on sides away from the electrode Yi.
With the first mode, since, when a voltage is supplied between the electrodes Xo and Yi for instance, the electric field above the electrode Xo becomes more intense on the metal electrode side, the pixel area can be increased essentially compared to a case in which the metal electrode is formed along the central line on the transparent electrode, even if the electrode pitch is reduced to achieve higher definition. This does not present any problem, since the sides of the electrodes Xo and Xe, which are opposite to the electrode Yi, are non display lines, and as the non display lines can be narrowed essentially, this is desirable.
In the second mode of the second aspect of the present invention, the electrodes Xo, Yi and Xe have substantially symmetrical forms relative to a central line of the electrode Yi; the electrode Yi is a metal electrode formed at the substrate; each electrode Xo and electrode Xe has a transparent electrode formed at the substrate, and a metal electrode formed at the transparent electrode at a width smaller than that of the transparent electrode; and the metal electrodes of the electrodes Xo and Xe are arranged on sides away from the electrode Yi.
With the second mode, since the width of the electrode Yi becomes small, the power consumption of supplying scanning pulses to the electrode Yi is reduced. In addition, it is possible to further reduce the pixel pitch.
In the third aspect of the present invention, there is provided a plasma display panel comprising substrate sustaining electrodes, for sustaining discharge, formed in parallel to one another at the substrate and address electrodes formed at the substrate or at another substrate facing the substrate at a distance, the address electrodes being arranged intersecting the sustaining electrodes at a distance in parallel to one another, the plasma display panel further comprising a light blocking member at a non display line between adjacent electrodes of the sustaining electrodes.
With the third aspect, by employing the light blocking member, reduction of the black display quality caused by discharge light emission at the non display line can be decreased.
In the first mode of the second aspect of the present invention, the address electrodes are covered with phosphor, and an observer-side surface of the light blocking member has darker color than the phosphor.
With the first mode, since incident light from the outside to the phosphor at the non display line is absorbed by the light blocking member, the contrast of an image on the PDP in a bright place increases more than a case that incident light from the outside to the phosphor at the non display line is reflected and enters eyes of an observer.
In the fourth aspect of the present invention, there is provided a plasma display apparatus comprising: a plasma display panel having a substrate, electrodes X1 to Xn formed at the substrate, electrodes Y1 to Yn formed at the substrate, address electrodes formed at the substrate or at another substrate facing the substrate at a distance and a light blocking member between electrodes Yi and Xi+1, where i=1 to nxe2x88x921, electrodes Xi and Yi being arranged by turns in parallel, where i=1 to n; and an electrode drive circuit; wherein the electrode drive circuit includes: reset means, for i=1 to nxe2x88x921, for causing a discharge to occur between the electrode Yi and an electrode Xi+1 while ensuring that voltage waveforms applied to the electrodes Xi and Yi are in the same phase to each other and that voltage waveforms applied to the electrode Xn and the electrode Yn are in the same phase to each other in a reset period; addressing means, for i=1 to n, for causing an address discharge to occur between either the electrode Xi or Yi and the address electrode selected in correspondence to display data and causes a discharge to occur between the electrode Xi and electrode Yi using the address discharge as a trigger to generate a wall charge required for a sustaining discharge in correspondence to the display data in an address period after the reset period has elapsed; and sustaining means, for i=1 to n, for supplying an AC sustaining pulse between the electrode Xi and the electrode Yi in a sustain period after the address period has elapsed.
With the fourth aspect, by employing the light blocking member, reduction of the black display quality caused by light emission during a reset period can be decreased. Although the light blocking member will somewhat prevent achieving higher definition, in comparison to the structure in the prior art shown in FIG. 30, since it is not necessary to form the partitioning walls 191 to 196, production is facilitated and the pixel pitch can be further reduced.
In the fifth aspect of the present invention, there is provided a plasma display panel comprising a substrate, address electrode bundles formed along to one another at the substrate and scanning electrodes, for causing a discharge between the address electrode bundles and the scanning electrodes to generate a wall charge required for a sustaining discharge in correspondence to display data, the scanning electrodes intersecting the address electrode bundles at a distance, wherein each of the address electrode bundles includes: m (mxe2x89xa72) number of address electrodes formed along to one another at the substrate in correspondence to one monochromatic pixel column; pads arranged along a lengthwise direction of the address electrodes corresponding to each monochromatic pixel, the pads being above the m number of address electrodes relative to the substrate; and contacts for connecting one pad to one of the address electrodes in a regular manner along the lengthwise direction of the address electrodes.
In the fifth aspect, by selecting m number of the scanning electrodes intersecting the pads connected to the m number of address electrodes simultaneously; and by applying voltages corresponding to display data to the m number of address electrodes simultaneously; scanning of the scanning electrodes is executed in units of m lines.
With the fifth aspect, a plurality of lines can be addressed at the same time, reducing the address period and, because of this, a higher number of gradations becomes possible by increasing the number of subfields or it becomes possible to achieve higher brightness by increasing the number of times sustaining discharge is performed.